This section varies quite a bit on your BIOS version and brand. The avialable optiosn also depends alot on technology, as newer boards using newer chipsets have mostly different options than boards using older chipsets. This is just one of those things that have to be dealt with. I will try to list as many options as I can for all BIOS. they may apply to you or they may not.

• Automatic Configuration
  Easiest setting. BIOS determines all of these settings for you.


• Read/Write Wait States
  Since the CPU is usually much faster than the memory, wait states are used to keep the memory in-tune with the faster CPU and thus avoid parity errors.


• DRAM Read/Write Burst
  Set the timing for burst-mode reads/writes from DRAM. The lower the timing numbers, the faster the system addresses memory. Selecting timing numbers lower than the installed DRAM is able to support can result in memory errors.


• DRAM R/W Leadoff Timing
  Select the combination of CPU clocks the DRAM on your board requires before each read from or write to the memory. Changing the value from the setting determined by the board designer for the installed DRAM may cause memory errors.


• DRAM Fast Leadoff
  Select Enabled to shorten the leadoff cycles and optimize performance.


• Fast EDO Leadoff
  Select Enabled only for EDO DRAMs in either a synchronous cache or a cacheless system. It causes a 1-HCLK pull-in for all read leadoff latencies for EDO DRAMs (i.e., page hits, page misses, and row misses). Select Disabled if any of the DRAM rows are populated with FPM DRAMs.


• Turbo Read Leadoff
  Select Enabled to shorten the leadoff cycles and optimize performance in cacheless, 50-60 MHz, or one-bank EDO DRAM systems.


• DRAM Speculative Leadoff
  A read request from the CPU to the DRAM controller includes the memory address of the desired data. When Enabled, Speculative Leadoff lets the DRAM controller pass the read command to memory slightly before it has fully decoded the address, thus speeding up the read process.


• Fast EDO Path Select
  When Enabled, a fast path is selected for CPU-to-DRAM read cycles for the leadoff, providing the system contains EDO DRAMs. It causes a 1-HCLK pull-in for all read leadoff latencies (i.e., page hits, page misses, and row misses).


• Turn-Around Insertion
  When Enabled, the chipset inserts one extra clock to the turn-around of back-to-back DRAM cycles.


• DRAM RAS# Precharge Time
  The precharge time is the number of cycles it takes for the RAS to accumulate its charge before DRAM refresh. If insufficient time is allowed, refresh may be incomplete and the DRAM may fail to retain data.


• Fast MA to RAS# Delay
  The values in this field are set by the system board designer, depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU.


• MA Additional Wait State
  Selecting Enabled inserts an additional wait state before the beginning of a memory read. The setting of this parameter depends on the board design. Do not change from the manufacturer’s default unless you are getting memory addressing errors.


• DRAM Page Idle Timer
  Select the amount of time in HCLKs that the DRAM controller waits to close a DRAM page after the CPU becomes idle.


• DRAM Enhanced Paging
  When Enabled, the chipset keeps the page open until a page/row miss. When Disabled, the chipset uses additional information to keep the DRAM page open when the host may be “right back.”


• SDRAM Speculative Read
  The chipset can “speculate” on a DRAM read address, thus reducing read latencies. The CPU issues a read request containing the data memory address. The DRAM controller receives the request. When this field is Enabled, the controller issues the read command slightly before it has finished decoding the data address.


• SDRAM (CAS Lat/RAS-to-CAS)
  You can select a combination of CAS latency and RAS-to-CAS delay in HCLKs of 2/2 or 3/3. The system board designer should set the values in this field, depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU.


• Refresh RAS# Assertion
  Select the number of clock ticks RAS# is asserted for refresh cycles.


• DRAM Refresh Queue
  Enabled permits queuing up to four DRAM refresh requests, so DRAM can refresh at optimal times. Disabled makes all refreshes priority requests. Installed DRAM must support this feature; most do.


• DRAM RAS Only Refresh
  An alternate to CAS-before-RAS refresh. Leave Disabled unless your DRAM requires this older method of refresh generation.


• DRAM Refresh Rate
  Select the period required to refresh the DRAMs, according to DRAM specifications.


• Fast DRAM Refresh
  The cache DRAM controller offers two refresh modes, Normal and Hidden. In both modes, CAS takes place before RAS but the Normal mode requires a CPU cycle for each. On the other hand, a cycle is eliminated by “hiding” the CAS refresh in Hidden mode. Not only is the Hidden mode faster and more efficient, but it also allows the CPU to maintain the status of the cache even if the system goes into a power management “suspend” mode.


• Read-Around-Write
  DRAM optimization feature: If a memory read is addressed to a location whose latest write is being held in a buffer before being written to memory, the read is satisfied through the buffer contents, and the read is not sent the DRAM.


• Memory Hole At 15M-16M
  An old feature that allowed you to set off 1 MB of memory for use by an ISA card. Most ISA cards, if you can still find them, don’t use this anyway.


• PCI Burst Write Combine
  When this option is Enabled, the chipset assembles long PCI bursts from the data held in these buffers.


• PCI-To-DRAM Pipeline
  DRAM optimization feature: If Enabled, full PCI-to-DRAM write pipelining is enabled. Buffers in the chipset store data written from the PCI bus to memory. When Disabled, PCI writes to DRAM are limited to a single transfer per write cycle.


• SDRAM RAS-to-CAS Delay
  Default is to have no delay. CAS stands for Column Access Strobe. DRAM is organized into rows and columns. Each area is accessed through strobes. When a memory access is performed by the CPU, it activates RAS (Row Access Strobe) to find the row containing the needed data. then, a CAS specifies the specific column to show the exact data needed. RAS speed is the speed of the chip, while CAS is half that speed. The delay setting tweaks the delay between the two signals that control the RAS and CAS. The number dictates how many CPU clock cycles the memory needs in order to prepare for another access. A setting of 3 is normal, but decreasing to 2 might speed up performance. As usual, if this results in any instability, change it back to 3.


• System BIOS, Video BIOS, Video RAM Cacheable
  This setting copies this data into the L2 cache, thus increasing performance. Problem is that Windows hardly ever uses this feature. So, it is recommend that these options remain disabled so as to preserve L2 space.


• Passive Release
  Controls whether the CPU can read and write to the PCI bus concurrently over the ISA bus. Enabling this enables the chipset’s embedded 32-bit posted write buffer to support delayed transaction cycles. This means that transactions to and from the ISA bus are buffered and the PCI bus can be freed to perform other transactions while the ISA transaction is underway. This allows you to meet PCI 2.1 specs. Sometimes this is called PCI 2.1 Compliance in the BIOS.


• Spread Spectrum Modulated
  Enabling this allows the system to turn off the AGP, PCI, and SDRAM signals when not in use in order to reduce electro-magnetic interference. Award says this can lead to some instability, so it should be disabled unless you’re having an EMI problem.


• Auto Detect DIMM/PCI Clk
  If enabled, the chipset will auto-detect if the DIMM and PCI sockets have devices attached and will send clock signals to each of them. If disabled, it will send clock signals to all DIMM and PCI sockets.

AGP & P2P Bridge Control

• AGP Aperture Size
  This setting controls just how much system RAM can be allocated to AGP for video purposes. Usually set anywhere from 1/4 to 1/2 of your total system RAM amount, depending on the amount of memory you have.


• AGP Mode
  Allows you to control the type of AGP used: 1X, 2X, 4X and 8X, depending on the specs supported by your motherboard. Set it to the highest your video card will support.


• AGP Driving Control
  Enables or disables the use of the following setting. Called AGP Comp. Driver in AMIBIOS. See next option.


• AGP Driving Value
  A feature of Via chipsets that allows manual control over the strength/timing of the AGP signal to the video card. It is more or less a workaround by Via to accomodate some areas of AGP that it is just not as good at as Intel. On 1X and 2X AGP cards, this is a non-issue. With higher-speed cards, it can become an issue. The available values are in hex format. Usually, this is left set to AUTO. If you need to use it to make your video card stable, the best bet is to contact the manufacturer to see what they recommend for a driver value.


• AGP Master 1 WS Write/Read
  When enabled, writes/reads to the AGP port are executed with one wait state. Usually, two are used, although some motherboards come with no wait states used, in which case this setting can hinder performance.


• AGP Fast Write Transaction
  Allows data to be sent directly from the corelogic (i.e. chipset) to the AGP master (graphics chip) instead of keeping a copy in system memory and making the AGP master fetch it. Can be enabled on 4X and higher cards for better performance.


• AGP Sideband Support
  AGP Sideband Addressing is a transfer mechanism allowing the requesting and receiving of data to occur at the same time. It may decrease stability and cause crashes on the Savage3D, due to the design of some motherboards resulting in glitches on strobes.

CPU & PCI Bus Control

• PCI 1/2 Master 0 WS Write
  Controls whether writes to the PCI bus are done with zero wait states or not. Enabled by default on many boards.


• PCI Post Write
  When this field is Enabled, writes from the CPU to the PCI bus are buffered, to compensate for the speed differences between the CPU and the PCI bus. When Disabled, the writes are not buffered and the CPU must wait until the write is complete before st arting another write cycle.


• PCI Delay Transaction
  The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1.