This is probably one of the most confusing parts of the processor to understand. The processor pipeline is like a conveyor belt. Now, imagine that instructions for the processor to carry out is food. The way a pipeline works is like this: the food moves along the conveyor belt, and when it gets to the other end of the conveyor belt that instruction is done. That is the simple way, but that is not technically correct. The way it works is this, (can’t think of any other way to explain it here) an instruction is fetched from the cache, then it continues to a different part of the pipeline, and so on. There are lots of different pipeline sizes, it all depends on what processor you have. This will explain how AMD manages to perform against Intel, even though Intel has a much higher clock speed than AMD.

The different parts of the pipeline perform different jobs. Some parts of the pipeline are duplicated, and adds to the length of the pipeline. Also, there can be more than one pipeline, which is why modern processors are said to have a super scalar architecture. The reason parts of the pipeline are duplicated is so less work has to be done at each stage. This means more instructions are completed in the same amount of time, speeding up performance. This is one of the key reasons AMD is able to contend with Intel. AMD Athlon XP’s have 3 X86 decoders, 3 floating-point pipelines, and 3 integer pipelines. This is compared with Intel’s Pentium 4, which has only one X86 decoder, 2 floating-point pipelines, and 1 more integer pipeline than AMD’s Athlon. This leads to AMD being able to decode more instructions than Intel at the same time, and being able to perform floating-point operations quicker than Intel. Overall, AMD Athlon XP processors are able to perform 9 operations per clock cycle while Intel can only manage 6. It doesn’t sound like much, but in processors every operation is crucial. This is why I said AMD are more about getting more done per clock cycle in my AMD processor buying guide.

This doesn’t mean it’s all over for Intel though. Even though AMD manages to perform more operations than Intel in one clock cycle, Intel manages to do their operations quicker. This is because of their pipeline architecture. AMD’s pipeline is only 10 stages long. This means that because the stages in the pipeline have to do more work, they can’t run very fast. Now, with Intel, their processors have a 20 stage pipeline (Prescott core processors have 31 stages). This means that the processor can run at a higher clock speed, because less work is done in each stage of the pipeline. The reason the Prescott core has been released is because this brings yet more speed. Because there are 31 stages, even less work is done, which means even higher clock speeds.

This can be linked to CISC computing and RISC computing. CISC stands for complex instruction set computing, and RISC stands for reduced instruction set computing. RISC means having less complex instructions for the processor. Here is an example of CISC giving someone commands. With CISC it would look like this:

1. Get food
2. Get fork
3. Eat

But with RISC it would be like this:

1. Go to kitchen
2. open fridge
3. get food
4. close fridge
5. open drawer
6. get fork
7. close drawer
8. open mouth
9. put food in mouth
10. close mouth
11. chew
12. swallow

The reason the CISC is more complex is because the processor has a lot more to do in one instruction. RISC is more efficient because it is very simple instructions, meaning less “thinking” is needed to perform the instruction, resulting in faster speed. Also, using RISC means there is less transistors needed in a processor, reducing cost. This is why all modern processors are RISC processors. But there is something you should know about X86 (the way the instructions are coded). X86 is actually built using a CISC architecture. This is why the processors need X86 decoders, to convert the CISC instructions into RISC instructions.

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