I think the problem boiled down to "swamping" of the memory bus. Look at it like this:
2 devices and one O/S fighting for memory space and the CPU doing all the work.
In my eyes, the best way to overcome these problems is a re-designed memory bus.
I saw a "beta" board by ALR that used 2 DIMMS for high and low addressing. To the system board, 8ns memory was used as though it were 4ns memory. This is a variatin of memory interleaving used on 386/486 system boards. The down side is that system memory is 1/2 of installed memory. The high side is that memory bus speeds are doubled and thus the access rate. Effective CAS/RAS timings are 1-1.5...thats speedy!
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